One may use the blocking transport calls of TLM2. Minimum timing details corresponding to the IP functionality, which are necessary for the embedded software, are modeled as well. In addition, it is possible to create these models without using any SystemC thread or by using a minimum number of threads. The IP model may realize the delay by calling wait, or by using the threads sensitive to timed events. If the delay stems from register access or a functionality corresponding to register access, then instead of realizing the delay, the IP model can send the delay back to the initiator by updating the annotated timing argument of the blocking transport call.
Due to context switching, multiple threads result in slow simulation. Use of temporal decoupling can enhance the system speed by reducing the amount of context switching between threads. Temporal decoupling allows a thread to run ahead of simulation time by keeping track of time through a local variable, and then sync up with the simulation kernel when Quantum has been reached. More accurately timed models are created by using the non-blocking interface of TLM2. The functionality of the IP can also be modeled with accurate timing details.
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These IP models are created with multiple SystemC threads to emulate the real concurrent operation of real hardware with their timing detail. These models are not suitable for the purpose of embedded software development. Memory is a very important component in a SoC. Due to high memory access traffic, the number of transport calls will be very high and that will have an impact on the simulation speed. Calling the wait frequently can have severe impact on the simulation speed.
Instead of realizing the delay itself, the memory model should send the annotated delay to the initiator through the transport call argument. This will provide the flexibility to the initiator to use temporal decoupling so that instead of calling wait after every transport call, it may sync up after many transport calls. Wrapping the processor model in a TLM2. Processor models come from the processor companies or the virtual platform tool vendors.
There also are some open-source processor models also available OVP, Qemu, etc. There can be different kinds of processor models. ISS models also can be cycle-accurate for use in the virtual platform with accurate timing details, or they can be untimed models for use in the virtual platform at a higher abstraction level for embedded software development. The tool chain of the target processor compiles the embedded software that will run on the virtual platform. The instruction set simulator reads the instruction set of the target CPU and generates host instructions to simulate those target instructions in the virtual platform.
It also maintains the internal state of the processor registers.
FPGA and SoC Design Expertise | Systems4Silicon
However, runtime translation of code on an instruction-by-instruction basis will result in a slow simulation; this is a consequence of the ISS speed, which is slow compared to the host processor. Applying various optimization techniques in the ISS may enhance the simulation speed. For example, QEMU uses the caching of runtime-translated instructions.
Then there are non-ABI-compliant processor models, which require native compilation. In such an approach, the target software running on the virtual platform is compiled with a special native compiler that translates the target software code into the instruction set of the host computer to simulate the behavior in the virtual platform. Because no runtime code translation is applied, this approach results in fast system simulation. Such systems require more time to design and develop. Communications in the context of an SoC can be divided into two categories.
For one, there is on-chip communication between the various IP blocks, and for another, there are the external interfaces for communicating with peripheral devices. SoCs consist of one or more processor cores and numerous other IP blocks. All these blocks transfer data amongst themselves by means of pins and wires. When creating the models at higher abstraction levels, we need not create the pin-level interface. Instead, we can conduct the data transfer using high-level function calls using transaction-level models TLMs.
TLMs provide a huge performance enhancement compared with pin-level models. Most of the SoC uses some flavor of memory-bus protocol through which the processor core master communicates with all other IP blocks slaves. However, while creating the models at higher abstraction levels, these lower-level functional and timing details need not be modeled. The Open Core Protocol provides a configurable set of features that is a superset of the features delivered with any memory-mapped SoC bus.
The standard interface allows the IP cores to connect with any SoC bus. The TL2 and TL1 abstraction levels are the lower abstraction levels, which model the finer protocol details functionality and timing as per the OCP protocol. When creating models for the purpose of embedded software development, it is sufficient to create the models at the TL4 abstraction level. It will allow you to refine the virtual platform to lower abstraction levels by simply replacing the TL4 sockets with lower abstraction sockets TL2 and TL1 , or by using the proper adaptors, thus making the virtual platform suitable for RTL verification, architectural exploration, and so on.
Apart from the pins corresponding to memory-mapped communication, the IP blocks in an SoC may also have other pins for communication, such as the interrupt line of an interrupt controller or the gate input of a timer. These are individual pins that cannot be clubbed with other pins to form a communication protocol. Communication through these SystemC ports is based on the events and update cycle of the SystemC scheduler, which impacts the simulation performance.
More signals means greater degradation of simulation speed. Further, when creating abstract models of such pins, it is advisable to use the function calls for the communication instead of using the pins themselves. You may define a TLM interface that can carry the value of the signal through a payload variable. In this case, you define a new TLM protocol for each signal; the connection is made through a one-to-one initiator and target socket connection. To do so, add a payload data member or each signal as a payload extension. In this case a bus will have to be used to route the signal from initiator to target, as all the initiator sockets of the IP blocks will connect to the target socket of the bus while all the target sockets of IP blocks will connect to the initiator sockets of the bus.
Using the bus instead of one-to-one connections does not provide any performance advantage, but it may provide some convenience in making the connections. However, that convenience comes at the cost of defining a more complex TLM protocol and modeling an extra component the bus. This makes sense only if there are many such signals in the SoC. An SoC also provides interfaces for communicating with external devices. At higher abstraction levels, there is no need to model these protocols in bit-accurate or cycle-accurate fashion to achieve similarity to the actual physical media.
Instead, we can transmit complete packets using function calls and annotated timings. While creating the models of IP blocks that use these communication protocols, there is no need to create the pin-accurate models. While the TLM protocol must be defined for each of these communication protocols, all the IP pins corresponding to the communication is abstracted away by TLM sockets. TLM protocols for each of these communication buses have to be defined for creating their models at higher abstraction levels.
The focus of this article is use of virtual platforms at higher abstraction levels for the purpose of embedded software development; this requires creating the untimed or loosely timed models using the blocking interface of OSCI TLM2. Thus, while extending TLM2. Extending TLM2. The payload will have the variables corresponding to TLM commands similar to read and write in base protocol , the transmitted data, and the control signals for handshaking protocol associated with those commands.
If we want to create more timing-accurate models approximate-timed or cycle-accurate at lower abstraction levels, we will need to use the non-blocking interface of TLM2. In such cases, we will also have to define the phases corresponding to the timing points in a transaction.
The number of phases will depend on the number of timing points in a given transaction. For greater timing accuracy, we will need more timing points and hence more phases. One can also define different interfaces function calls and protocols for each non-memory-mapped bus. Moreover, extending TLM2. That means models from different vendors cannot be connected out of the box, and some kind of adaptors will have to be created to connect them.
The industry needs a standardization initiative for defining standard TLM protocol for the popular non-memory-mapped buses.
SoC & FPGA Development
However, extending TLM2. SoCs with a specific non-memory-mapped interfaces will have the controller IP corresponding to that interface. This interface-specific socket connects with an external device. The external device should also understand the same TLM protocol. When creating models of such IP blocks, you will need a generic back end to handle the interface-specific TLM communication for the external device.
The model of the external device can use this generic backend component and implement the device specific functionality. If an external bus interface allows ultiple connections, then you should create a virtual bus model router that allows connecting multiple devices through the interface-specific TLM socket.
Such a layered approach allows connecting the virtual platform with different kind of backbends virtual model of the external device, physical interface on host computer or the RTL of external device, and so on. Any SoC provides the interfaces for connecting with the external devices. The embedded software running on the SoC can access the external devices through these interfaces. While creating the virtual platform of a SoC, one of the challenges is how to test these external interfaces.
One mechanism is to create the SystemC models of the external devices and connect these device models with the SoC through the TLM sockets corresponding to these external interfaces. The embedded software running on the virtual platform will access the software models of these external devices. This is not the best mechanism; for testing the real software, the best way is to use the real external device.
The host computer on which the virtual platform executes provides some general-purpose interfaces such as USB and Ethernet. If we can access these physical interfaces of the host computer in the virtual platform, then the software running on the virtual platform will be able to communicate with the real-world physical devices.
This provides a very powerful virtualization environment for testing the embedded software. Let us look at how to access a USB port of the host computer inside the virtual platform. The standard USB driver in the guest operating system running on the virtual platform should work fine with the model of the host controller just as it does with the real host-controller hardware.
The latter acts as a USB application in the user space of the host computer. Similarly, we can access any other interface available on the host computer Ethernet, WLAN, printer, speaker, microphone, LCD screen, camera, and so on.
Embedded Software for Soc
One of the advantages of using a virtual platform for embedded software development instead of using the FPGA board is that the virtual platform provides powerful debugging features. With use of multicore systems on the rise, debugging such systems and reproducing bugs in them can be very challenging. Virtual platforms make the debugging of applications much easier; it provides better visibility into hardware and software simultaneously at run time.
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Embedded software in the SoC world. With increasing SoC complexity, SoC designers are facing an increasing complexity in the system's architecture other than the HW issues alone. The intricacy of the software needed to run on such devices is increasing tremendously as well.